The present invention relates to a capacitor fabricating method of a semiconductor device, and more particularly, to a capacitor fabricating method of a semiconductor device in which a ridge and valley-type lower electrode is formed using a hemispherical grained silicon (HSGxe2x80x94Si).
A decrease in cell capacitance according to the decrease of cell memory area is an obstacle to the increase in stability of a dynamic random access memory (DRAM). The decrease in cell capacitance lowers the reading and writting abilities of the memory cell, increases the soft error ratio, and further disturbs the operation of the device at lower voltages. Thus, for high integration of the semiconductor memory device, the decrease in cell capacitance should be overcome.
Generally, in 64Mb DRAMs having a memory cell area of approximately 1.5 xcexcm2, it is difficult to provide sufficient capacitance even when a dielectric substance such as Ta2O5 is used in a general stacked-type capacitor having a two-dimensional structure. Thus, recently, a capacitor having a three-dimensional structure has been suggested to increase cell capacitance, such as a lower electrode having a fin structure (Fujitsu), a lower electrode having a box structure (Toshiba), a lower electrode having a cylindrical structure (Mitsubishi), etc.
However, in the case of the capacitor having a three-dimensional structure, the fabrication process thereof is complicated and a defect may occur in the fabrication process, thus applying such structure is difficult. Also, research into a high dielectric film has been conducted in order to increase the capacitance of the capacitor, however, the high dielectric film has many problems in application. Thus, research into a method for fabricating a ridge and valley-type lower electrode, in which area is locally increased, has been performed to increase capacitance.
In one method of fabricating the ridge and valley-type lower electrode, multiple bumps of HSGxe2x80x94Si are formed on the surface of the lower electrode to form ridges and valleys in the surface thereof, thereby increasing the surface area of the lower electrode.
As a method for forming HSGxe2x80x94Si on the surface of the lower electrode, there are following methods: 1) a chemical vapor deposition method in which silicon is deposited at a temperature where phase transformation occurs from amorphous silicon to polysilicon, 2) a method for annealing amorphous silicon without native oxide layer in a vacuum, and 3) a seeding method in which HSGxe2x80x94Si seeds are formed by a low pressure chemical deposition (LPCVD) method using SiH4 or Si2H6 gas, or by irradiating SiH4 or Si2H6 beam on the amorphous silicon, and then the formed seeds are grown.
It has been reported that the surface area of the lower electrode is effectively increased when the ridge and valley-type silicon lower electrode is formed using the seeding method in an article by H. Watanabe et al., A New Cylindrical Capacitor Using HSGxe2x80x94Si for 256Mb DRAMs, IEDM ""92, pp. 259-262.
FIGS. 1 through 3 are cross-sectional diagrams for illustrating a conventional method for fabricating a capacitor of a semiconductor device.
FIG. 1 is a cross-sectional diagram for illustrating the step of forming an insulation layer pattern 20 and a lower electrode 40. First, an insulation layer such as a silicon oxide layer is formed on a semiconductor substrate 10 and then the insulation layer is patterned by a photolithography process to form the insulation pattern 20 having a contact hole which exposes a predetermined area of the semiconductor substrate 10.
Subsequently, after an amorphous silicon layer doped with impurity is formed on the entire surface of the substrate having the insulation later pattern 20 to fill the contact hole, the resultant structure is patterned by a general method. As a result, the lower electrode 40 having a cylindrical structure is formed on a predetermined area of the insulation layer pattern 20, which is connected to the exposed semiconductor substrate via the contact hole.
FIG. 2 is a cross-sectional diagram for illustrating the step of forming HSGxe2x80x94Si seeds 50a and 50b, wherein the HSGxe2x80x94Si seeds are formed on the lower electrode 40 by a low-pressure chemical deposition (LPCVD) method using a silicon source gas. Here, since the HSGxe2x80x94Si seeds are formed first at a portion of the lower electrode 40 with high surface energy, the HSGxe2x80x94Si seeds are scattered on the surface of the lower electrode 40. Also, as the silicon source gas, SiH4, Si2H6, Si3H8, SiH2Cl2 or SiH2Cl2 is used.
Of course, the HSGxe2x80x94Si seeds may be formed on the lower electrode 40 by irradiating the silicon source gas as a beam on the entire surface of the substrate having the lower electrode 40.
Since the selectiveness of the HSGxe2x80x94Si seed formation process is very low, the HSGxe2x80x94Si seeds are formed on the insulation layer pattern 20 during the step of forming HSGxe2x80x94Si seeds on the lower electrode 40. Hereinafter, HSGxe2x80x94Si seeds formed on the lower electrode 40 will be referred to as first HSGxe2x80x94Si seeds 50a, and HSGxe2x80x94Si seeds formed on the insulation layer pattern 20 will be referred to as second HSGxe2x80x94Si seeds 50b, respectively.
FIG. 3 is a cross-sectional diagram for illustrating the step of forming HSGxe2x80x94Si 50c. Here, the substrate having the first and second silicon seeds 50a and 50b is heated to selectively grow the first HSGxe2x80x94Si seeds 50a, thereby forming the HSGxe2x80x94Si 50c on the lower electrode 40. As a result, the surface area of the lower electrode 40 is increased. Here, since the first HSGxe2x80x94Si seeds 50a grow by receiving silicon from the lower electrode 40 differently from the second HSGxe2x80x94Si seeds 50b which cannot receive silicon required for growth, only the first HSGxe2x80x94Si seeds 50a are grown.
Here, the second HSGxe2x80x94Si seeds 50b remain on the insulation layer pattern 20, so that the lower electrode 40 and a lower electrode of a capacitor adjacent thereto are electrically shorted, causing mis-operation of the semiconductor device. Also, since an increase in area at the lower electrode 40 depends only on the growth of the first HSGxe2x80x94Si seeds 50a, it is difficult to obtain sufficient cell capacitance for ensuring reliable operation of the semiconductor device.
Further, a dielectric layer and an upper electrode are formed in sequence on the entire surface of the substrate having the HSGxe2x80x94Si 50c to complete a capacitor, wherein this step is not shown.
As described above, in the conventional method for fabricating a capacitor of a semiconductor device, the second HSGxe2x80x94Si seeds 50b remain on the insulation pattern 20, so that the lower electrodes of each adjacent capacitors are susceptible to electrical shorts. Also, since the increase in area of the lower electrode 40 depends only on the growth of the first HSGxe2x80x94Si seeds 50a, there are difficulties in the ensuring sufficient cell capacitance. Thus, reliability of the semiconductor device is decreased.
To overcome the above problems, it is an object of the present invention to provide a method for fabricating a capacitor of a semiconductor device, which can improve reliability of the semiconductor device.
According to the first embodiment for achieving the object, there is provided a method for forming a capacitor of a semiconductor device comprising the steps of: (a) forming an insulation layer pattern on a semiconductor substrate, having a contact hole which exposes a predetermined area of the semiconductor substrate; (b) forming a lower electrode on a predetermined area of the insulation layer pattern, the lower electrode is connected to the exposed semiconductor substrate via the contact hole; (c) forming HSGxe2x80x94Si seeds on the surfaces of the lower electrode and the insulation layer pattern; (d) etching the surface of the lower electrode by using the HSGxe2x80x94Si seeds formed on the surface of the lower electrode as an etching mask to form a depressed portion on the surface of the lower electrode, resulting in the formation of a modified lower electrode; and (e) growing the HSGxe2x80x94Si seeds formed on the surface of the lower electrode to form multiple bumps of HSGxe2x80x94Si.
Here, the step (d) of etching the surface of the lower electrode is performed using a gas including chlorine, and the gas including chlorine is one selected from the group consisting of Cl2, BCl3, ClF3 and HCl.
Also, preferably, the step (d) of etching the surface of the lower electrode is performed by anisotropically etching while varying the incident angle of etching gas.
Preferably, the step (e) of growing the HSGxe2x80x94Si seeds is performed by heating the substrate having the HSGxe2x80x94Si seeds, and the heating is performed at 560xcx9c630xc2x0 C.
Also, it is preferably that the method for forming a capacitor of a semiconductor device further comprises the step of removing the HSGxe2x80x94Si seeds formed on the surface of the insulation layer pattern by an etching after the step (e). Here, the step of removing HSGxe2x80x94Si seeds formed on the surface of the insulation layer pattern by an etching is performed by using the gas including chlorine, and the gas including chlorine is one selected from the group consisting of Cl2, BCl3, ClF3 and HCl.
According to the second embodiment for achieving the object, there is provided a method for forming a capacitor of a semiconductor device comprising the steps of: (a) forming an insulation layer pattern on a semiconductor substrate, having a contact hole which exposes a predetermined area of the semiconductor substrate; (b) forming a lower electrode on a predetermined area of the insulation layer pattern, the lower electrode is connected to the exposed semiconductor substrate via the contact hole; (c) forming HSGxe2x80x94Si seeds on the surfaces of the lower electrode and the insulation layer pattern; (d) selectively growing the HSGxe2x80x94Si seeds formed on the surface of the lower electrode to form multiple bumps of HSGxe2x80x94Si on the surface of the lower electrode; (e) removing the HSGxe2x80x94Si seeds formed on the surface of the insulation layer pattern through an etching process.
Also, the step (c) of forming the HSGxe2x80x94Si seeds is performed by a chemical vapor deposition (CVD) method using a silicon source gas.
It is preferably that the step (d) of forming the HSGxe2x80x94Si is performed by heating the substrate having the HSGxe2x80x94Si seeds, and the heating is performed at 560xcx9c630xc2x0 C.
In addition, the step of removing the HSGxe2x80x94Si seeds formed on the surface of the insulation layer pattern by an etching is performed by using a gas including chlorine, and the gas including chlorine is one selected from the group consisting of Cl2, BCl3, ClF3 and HCl.
In the method for fabricating a capacitor of a semiconductor device according to the present invention, the surface area of the lower electrode is increased, so that a high cell capacitance can be ensured compared to that of the conventional device. Also, an electrical short between the lower electrodes of adjacent capacitors can be prevented without decreasing capacitance.